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NanoBlog

A blog about anything nanotech

Materials Project

morreale Wednesday 04 of January, 2017
Professor Kristin Persson from UC Berkeley give a very interesting talk on her groups efforts to build a materials properties database using the quantum mechanical codes on the high performance super computers at Lawrence Berkeley National Laboratory. There are about 70,000 inorganic compounds but there is only materials properties on only about 300-400 compounds. It took about a year to get the code to run on the super computer that would work well with the work flow of the user community. It the last 2 years, the project has generated 10 time the data that was previously available. The Materials Project database is open source and open access.

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The transistor turns 90

morreale Sunday 16 of October, 2016
The transistor turns 90 this year. An applications for the FET was file in October 1926 by Julius Edgar Lilienfeld. Lam Research has posted a tech brief on the transistor and how it has changed over time. The brief also describes the future of the transistor structure.

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The NanoHUB

morreale Friday 23 of September, 2016
Purdue University posted the video Mythbusting Nanotechnology Knowledge Transfer through novel Cyberinfrastructure which describes the history and impact of the nanoHUB. The video is almost a year old but provides some really interesting statistics on education, STEM demographics, income, the impact of education on income, and the process of building a user community that uses programs that were written for research.


ISSCC 2016 Keynote

morreale Saturday 10 of September, 2016
William M. Holt from Intel gave the ISSCC 2016 keynote talk entitled 1.1 Moore’s Law: A Path Forward. Holt's talk was very interesting and focused on the effort to minimize power dissipation at Intel and the industry. He also described technologies under dewvelopment that may appear in future nodes. Most of these new devices reduce power dissipation but do not provide speed increases, however. The energy-delay product of a device is the key metric used to compare power efficiency. The paper for the talk 1.1 Moore's law: A path going forward is also available at the IEEE.

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Image credit: EE Times Moore’s Law Goes Post-CMOS

Intel 10 nm FinFET process

morreale Saturday 10 of September, 2016
The Semiconductor Engineering website posted an interview with Mark Bohr senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry. In the article, we learned that
  • 10 nm will be a full node for Intel
  • 10 nm devices will be full production around 2H 2017
  • Some design rules are scaling is better than 0.56x
  • Uses 193nm immersion and self-aligned double patterning