7 nm Model Parameters
Since the frequency response in homework 2 produced a unity gain frequency for the shorter gate length that wasn't higher than the long gate length FinFET, I suspect a problem with the model or the way I'm using it so I investigated the model further. The following model parameters were used for this investigation and for homework 3.parameter | Model | Value | units |
Fin Length | L | 20.0 | nm |
Number of fins | NFIN | 3 | |
Number of fingers | NFGR | 1 | |
Fin Height | HFIN | 32.0 | nm |
Fin Thickness | TFIN | 6.5 | nm |
Fin Pitch | FPITCH | 27.0 | nm |
Fin Width, 1 fins | W | 70.5 | nm |
Fin Width, 3 fins | 211.5 | nm | |
W/L for 3 fins | 10.6 | ||
Gate oxide thickness | EOT | 1 | nm |
The fin width was computed as NFIN (2 HFIN + TFIN) where HFIN is the fin height and TFIN is the fin thickness using the .model variables. This makes W/L = 10.6 for a FinFet with 3 fins.
Extracted 7 nm lvt Model Parameters by Simulation
Using methods described in the course and in the book, the performance parameters for the 7 nm models were extracted. I haven't found a references to confirm the performance values yet.
Parameter | NMOS | PMOS | Units |
μC_{OX} | 156.6 | 110.2 | μA/V^{2} |
V_{t} | 230 | -210 | mV |
λ | 0.1795 | 0.3563 | 1/V |
λL | 0.0036 | 0.0071 | μm/V |
C_{OX} | fF/μm^{2} | ||
n | 1.05 | 1.02 | |
θ | 2.94 | 1.92 | V |
C_{OV}/W = L_{OV}C_{OX} | 0.16 | 0.16 | fF/μm |
C_{db}/W ≈ C_{Sb} | 5.5*10^{-8} | 5.6*10^{-8} | fF/μm |
The 7 nm models from the PTM website [1] are define with the .model function and have more parameters defined compared to the modified (simplified) model provided for the course. These models use the BSIM-CMG [2] model. The PTM website indicates that the model process maximum supply voltage is 700 mV. The homework, however, specifies V_{DS} = 800 mV in the problems so was used for the solutions. The solutions are based on the materials presented in the course and the book Analog Integrated Circuit Design [3].
The sections below show how the parameters were determined and how the SIMetrix simulator was setup to make the measurements. Mathematica was used to add the line guides to estimate the projection of the g_{m} slopes to the x-axis and to the projections of maximum g_{m}.
NMOS μ_{n}C_{OX}, V_{t}, subthreshold slope, n, and θ
The schematic used for finding μ_{n}C_{OX}, V_{t}, subthreshold slope, n, and θ is shown below.
The top plot in the figure below shows g_{m}/I_{D} vs V_{GS}. The minimum was found to be 62.4 mV/decade using
Measure -> 8 Minimum
. n=1.05 was found using Ln(10)(nKT/q) = subthreshold slope (i.e n = 62.4 mV/(2.3kT/q)).The middle plot shows g_{m} vs V_{GS}. The linear slope of g_{m} is μ_{n}C_{OX}(W/L) and was used to determine μ_{n}C_{OX} at 156.6 μA/V^{2} for W/L = 211.5/20. The projection of the slope to the x-axis gives V_{t} at 230 mV. The voltage V_{GS} at the intersection of where the projection of the g_{m} slope to a line that is parallel to where g_{m} flattens is used to determine V_{eff}. At that point V_{eff} = 1/(2θ). Solving for θ, θ = 2.9/V [4].
The bottom plot shows I_{D} in the active region.
PMOS μ_{p}C_{OX}, V_{t}, subthreshold slope, n, and θ
The schematic used for finding μ_{p}C_{OX}, V_{t}, subthreshold slope, n, and θ is shown below.
The top plot in the figure below shows g_{m}/I_{D} vs V_{GS}. The minimum was found to be 60.8 mV/decade using
Measure -> 8 Minimum
. n=1.02 was found using Ln(10)(nKT/q) = subthreshold slope (i.e n = 60.8 mV/(2.3kT/q)).The middle plot shows g_{m} vs V_{GS}. The linear slope of g_{m} is μ_{p}C_{OX}(W/L) and was used to determine μ_{p}C_{OX} at 110.2 μA/V^{2} for W/L = 211.5/20. The projection of the slope to the x-axis gives V_{t} at 210 mV. The voltage V_{GS} at the intersection of where the projection of the g_{m} slope to a line that is parallel to where g_{m} flattens is used to determine V_{eff}. At that point V_{eff} = 1/(2θ). Solving for θ, θ = 1.9/V
The bottom plot shows I_{D} in the active region.
NMOS λL
The schematic below was used determine λ.
The top plot in the figure below shows g_{ds}/I_{D} and the bottom shows I_{D} vs V_{DS} for V_{GS} = 300 mV, 500 mV, 800 mV, and 1 V. To generate a useful plot g_{ds}/I_{D}, the
Choose Analysis
V_{DS} sweep can't start a 0 V so that g_{ds}/I_{D} doesn't become infinite.g_{ds}/I_{D} and I_{D} vs V_{DS} were plotted again but only for V_{GS} = 500 mV to determine λ and λL. Recall that
$$g_{ds}=\frac{\partial I_d}{\partial V_{DS}}=\lambda (\frac{\mu_n C_{OX}}{2})(\frac{W}{L})V_{eff}^2=\lambda I_{D-sat}=\lambda I_d$$
In short, g_{ds}/I_{D} = λ and was sampled in the middle of the active range at V_{DS} = 654 mV as the start of the active region occurs at V_{DS-sat} = V_{eff} = 500 mV - 230 mV = 270 mV. λ = 0.1795/V and λL = 0.00359 μm/V [5].
PMOS λL
g_{ds}/I_{D} and I_{D} vs V_{DS} were plotted again but only for V_{GS} = 500 mV to determine λ and λL. Recall that $$g_{ds}=\frac{\partial I_d}{\partial V_{DS}}=\lambda (\frac{\mu_p C_{OX}}{2})(\frac{W}{L})V_{eff}^2=\lambda I_{D-sat}=\lambda I_d$$
In short, g_{ds}/I_{D} = λ and was sampled in the middle of the active range at V_{DS} = 693 mV as the start of the active region occurs at V_{DS-sat} = V_{eff} = 500 mV - 210 mV = 290 mV. λ = 0.3563/V and λL = 0.00713 μm/V.
NMOS C_{OV}/W and C_{db}/W
The schematic below was used to determine C_{OV}/W.
The plot below shows the gate current I_{g} vs frequency. The gate current is function of frequency and I_{g} = 2πfV_{g}C_{OV}. Solving for C_{OV}, C_{OV} = I_{g}/(2πfV_{g}) with f = 10 MHz and V_{g} = 2 V because the AC source produces a 1 V peak output. I_{g} = 4.25 nA at 10 MHz so C_{OV}/W = 0.16 fF/μm for the 211.5 nm gate width [6].
The schematic below was used to find C_{db}/W.
The plot below shows the body current I_{b} vs frequency. The body current is function of frequency and I_{b} = 2πfV_{b}C_{b} where C_{b} = C_{db}+C_{sb}. Solving for C_{b}, C_{b} = I_{b}/(2πfV_{bs}) with f = 10 MHz and V_{b} = 2 V because the AC source produces a 1 V peak output. I_{b} = 2.95 fA at 10 MHz so C_{b}/W = 1.1*10^{-7} fF/μm for the 211.5 nm gate width. For C_{db} = C_{sb} = C_{b}/2 = 5.5*10^{-8} fF/μm [7].
PMOS C_{OV}/W and C_{db}/W
The schematic below was used to determine C_{OV}/W.
The
Simulate -> Choose Analysis
setup for the AC analysis shown below.I_{g} = 4.25 nA at 10 MHz so C_{OV}/W = 0.16 fF/μm for the 211.5 nm gate width.
The schematic below was used to find C_{db}/W.
I_{b} = 3.099 fA at 10 MHz so C_{b}/W = 1.13*10^{-7} fF/μm for the 211.5 nm gate width. For C_{db} = C_{sb} = C_{b}/2 = 5.57*10^{-8} fF/μm.
NMOS I_{D} and R_{in} vs V_{GS}
The gate and drain for the nmos_lvt and nmos_rvt transistors are connected together to simulated the IV curve of a diode connected transistor that is used as part of a current mirror. The MOSFET connected in this way isn't really a diode but its IV curve behaves like an diode IV curve because the V_{GS} = V_{DS} and the transistor operates in the active region. The I_{D} vs V_{DS} is
$$I_d=\frac{1}{2}\mu_n C_{OX} \frac{W}{L} (V_{GS}-V_t)^2 = \frac{1}{2} \mu_n C_{OX} \frac{W}{L}(V_{DS}-V_t)^2$$
Solving for V_{DS} gives [8]
$$V_{DS}=\sqrt{\frac{I_d}{\frac{1}{2} \mu_n C_{OX} \frac{W}{L}}}+V_t$$
Using the model parameters in the table above at 100 μA, V_{DS} = 577.5 mV$ for the nmos_lvt transistor, and V_{DS} = 609.2 mV$ at 100 μA in the simulation. This represents a 32 mV error between the simulation and the calculation.
Transistor | V_{DS} | Simulation | Units |
nmos_lvt | 577.5 | 609.2 | mV |
The schematic below shows the diode connected nmos_lvt and nmos_rvt FinFETs in single and stacted configurations.
The bottom plot in the figure below shows the I_{D} vs V_{GS} for the nmos_lvt and nmos-rvt transistors. The top two traces are the single gate-drain connected transistors, and the bottom two traces are the stacked transistors. The REF cursor is set at the I_{D} = 100 μA for the single nmos_lvt transistor. The B cursor is set at the I_{D} = 100 μA for the stacked nmos_lvt transistors. The middle plot shows g_{m} for the transistors. The single transistors have the higher g_{m} compared with the stacked transistors. The top plot shows the output resistance. The cursors was placed at 100 μA for the nmos_lvt device and the V_{DS} is 609.2 mV and an resistance of 6.093 kOhms. The stacked nmos_lvt transistors have a V_{DS} of 814.0 mV and a resistance of 8.138 kOhms.
PMOS I_{D} and R_{in} vs V_{GS}
The simulation was repeated for the pmos_lvt and pmos_rvt transistors for both single and stacked configurations. The schematic for this simulation is shown below.
The bottom plot in the figure below shows the I_{D} vs V_{GS} for the nmos_lvt and nmos-rvt transistors. The top two traces are the single gate-drain connected transistors, and the bottom two traces are the stacked transistors. The REF cursor is set at the I_{D} = 100 μA for the single nmos_lvt transistor. The B cursor is set at the I_{D} = 100 μA for the stacked nmos_lvt transistors. The middle plot shows g_{m} for the transistors. The single transistors have the higher g_{m} compared with the stacked transistors. The top plot shows the output resistance. The cursors was placed at 100 μA for the nmos_lvt device and the V_{DS} is 650.5 mV and an resistance of 6.505 kOhms. The stacked nmos_lvt transistors have a V_{DS} of 902.5 mV and a resistance of 9.021 kOhms.
The figures below shows how the
Choose Analysis
and Define Curve
configuration panels were setup to produce the plot above.Index
- Analog IC Design in Nanoscale CMOS Short Course
- Analog IC Design Course Homework 1 SIMetrix Edition
- Analog IC Design Course Homework 2 SIMetrix Edition
References
[1]: ASU Predictive Technology Model (PTM)
[2]: BSIM Group Berkeley BSIM-CMG Model
[3]: T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd Edition. Wiley, 2011.
[4]: T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd Edition. Wiley, 2011. see pg. 28, 30, 47.
[5]: T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd Edition. Wiley, 2011. see pg. 29.
[6]: 45nm CMOS process – Learning Microelectronics
[7]: 45nm CMOS process – Learning Microelectronics.
[8]: T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd Edition. Wiley, 2011. see pg. 129.