Skywater 130nm Advanced Process Design Workshop

morreale Thursday 11 of August, 2022

Sky130 Inverter Layout

efabless sponsored a workshop on Advanced Physical Design using the openLANE open source toolchain, and the Skywater 130 nm Physical Design Kit (PDK). Google and Skywater have been working to make custom semiconductor design and processing open source. The course was produced and taught by VLSI System Design (VSD) - Intelligent Assessment Technology (IAT).

The workshop was held August 2 to 6 and each day begins with an Q&A session at 10:30 AM ET over Zoom. The course lectures were recorded and made available on the VSD learning platform. The platform also provided a compute instance containing all the tools and PDK library all setup to use.

The platform was very responsive for both the lecture recordings and running the labs to learn the design toolchain. The workshop also provided a Slack workspace to interact with other students and get questions answered. The instructors were very good about responding to questions to help solve problems with simulations. The subjects covered each day are shown below. Each module also had exams.

  • Day 1 - Inception of open-source EDA, OpenLANE and Sky130 PDK
  • Day 2 - Good floorplan vs bad floorplan and introduction to library cells
  • Day 3 - Design library cell using Magic Layout and ngspice characterization
  • Day 4 - Pre-layout timing analysis and importance of good clock tree
  • Day 5 - Final steps for RTL2GDS using tritonRoute and openSTA

The first three days introduce you to the openLANE toolchain and the PDK. On the last two days, we replaced a standard cell inverter with a custom cell in the picorv32a design to demonstrate how to add a custom cell to an existing design. The picorv32a is a Size-Optimized RISC-V CPU core that executes the RISC-V RV32IMC Instruction Set. The sections below describe show my results produced from the workshop labs. The workshop is intense and required around 10 to 12 hrs/day to work through the lectures, labs and exams as this was my first introduction to an ASIC design toolchain.

There wasn't enough time to finish the timing optimization. Fortunately, the tools can be downloaded and installed on a local computer and completed offline. Designs can be submitted to the Google/Skywater Multi-Project Wafer (MPW) shuttle. The submission deadline is Sept 12, 2022. To learn more, please see my Skywater 130n Advanced Process Design Workshop report on GitHub. My certificate of completion is shown below.

sky130 APD Workshop Certificate of Completion