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The Analog IC Design in Nanoscale CMOS short course is scheduled for September 7 to October 1, 2021 virtually from the University of Limerick. The short course consists of eight 1.5 hour lectures followed by a half hour question and answer session. The course is taught by Professor Tony Chan Carusone.

• Course description(https://www.dropbox.com/s/yaeo6wvxee7wgv6/Tony_Chan_Carusone_Online_Training_Course_2021.pdf?dl=0)
• Course registration(https://www.linkedin.com/feed/update/urn:li:activity:6812699785666052096/)

Course Program

• Lecture 1 - CMOS Device Scaling & Modeling 7th Sept. 2021
  Device scaling, short-channel length effects, analog design on bulk CMOS technologies below 30nm.
• Lecture 2 - Advanced CMOS Technologies: SOI & FinFET 10th Sept. 2021
  Impact on transistor model parameters, analog FOM & layout strategies. Reliability effects.
• Lecture 3 - Amplifier Design in Nanoscale CMOS 14th Sept. 2021
  Design of current mirrors & amplifier circuits. Suitable OTA topologies for low supply-voltage.
• Lecture 4 - References, Regulators & Power Integrity 17th Sept. 2021
  Diff. reference circuits & voltage regulation. Power distribution in ICs. Power integrity analysis.
• Lecture 5 - Nanoscale CMOS Clocking 21st Sept. 2021
  Jitter sources, amplification & power-supply-induced jitter. CMOS buffering & clock distribution.
• Lecture 6 - Dynamic Comparators & Amplifiers 24th Sept. 2021
  Applications of dynamic amplifiers (as integrators) in high-speed receivers. Dynamic comparators.
• Lecture 7 - ADC-Based Receivers in Nanoscale CMOS 28th Sept. 2021
  High-speed ADCs: folding-flash, binary search & CT pipelined. Combatting mismatch & applications.
• Lecture 8 - Real-Life Cautionary Tales 1st Oct. 2021
  Common design & layout errors, integrating large designs, power & clock routing, non-working chips.

References

The following references provides some background for the course.

• Textbook chapter 1 for lectures 1 and 2
• Textbook chapter 7.4 for lecture 4
• IEEE articles shown below

Text Book

• Analog Integrated Circuit Design 2nd Edition(https://books.google.com/books/about/Analog_Integrated_Circuit_Design_2nd_Edi.html?id=GeobAAAAQBAJ) by Tony Chan Carusone

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Journal publications

• D. Mohammadi, et al, “A 7-GS/s 5-Bit Continuous-Time Pipelined Binary-Search Flash ADC in 28-nm CMOS(https://ieeexplore.ieee.org/abstract/document/9189840),” IEEE Solid-State Circuits Letters, Sept. 2020.
• B. Dehlaghi*, et al, “A 1.41pJ/b 56Gb/s PAM-4 Receiver Using Enhanced Transition Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS(https://ieeexplore.ieee.org/document/8821332),” IEEE Solid-State Circuits Letters, 2019.
• L. Wang, et al, “A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET(https://ieeexplore.ieee.org/abstract/document/8527524),” IEEE Journal of Solid-State Circuits, Dec 2018.
• L. Wang, et al, “A 4GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16nm FinFET(https://ieeexplore.ieee.org/abstract/document/7976362),” IEEE Transactions on Circuits and Systems II, Dec. 2017.
• S. Shahramian, et al, “Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5 us(https://ieeexplore.ieee.org/abstract/document/7563432),” IEEE Journal of Solid-State Circuits, pp. 3192-3203, Nov 2016.
• B. Dehlaghi, et al, “A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication(https://ieeexplore.ieee.org/abstract/document/7552548),” IEEE Journal of Solid-State Circuits, pp. 2690-2701, Nov 2016.
• D. Dunwell, et al, “Modeling Oscillator Injection Locking Using the Phase Domain Response(https://ieeexplore.ieee.org/abstract/document/6496169),” IEEE Transactions on Circuits and Systems I, 2013, pp. 2823-2833, November 2013.
• K. Yamamoto, et al, “A 1-1-1-1 MASH Delta-Sigma Modulator with Dynamic Comparator-Based OTAs(https://ieeexplore.ieee.org/abstract/document/6231697),” IEEE Journal of Solid-State Circuits, vol. 49, no. 8, pp. 1866-1883, August 2012.

Conference publications:

• P. Chen, et al, “All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs(https://ieeexplore.ieee.org/abstract/document/9180833),” IEEE International Symposium on Circuits and Systems, Seville, Spain, October 2020.
• S. Shahramian*, et al, “A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS(https://ieeexplore.ieee.org/abstract/document/8662421),” International Solid-State Circuits Conference, February 2019.
• S. Chen, et al, “All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters(https://ieeexplore.ieee.org/abstract/document/7932534),” International Symposium on Circuits and Systems, May 2018.
• S. Shahramian, et al, “Chip-Level Power Integrity Methodology for High-Speed Serial Links(https://www.eecg.utoronto.ca/~tcc/Shahramian_DesignCon_2018.pdf),” DesignCon, Santa Clara, California, January 2018.
• A. Sharif-Bakhtiar, et al, “Low-Power CMOS Receivers for Short Reach Optical Communication(https://ieeexplore.ieee.org/abstract/document/7993601),” Custom Integrated Circuits Conference, Austin, Texas, May 2017.
• L. Wang, et al, “Time Interleaved C-2C SAR ADC with Background Timing Skew Calibration in 65nm CMOS(https://ieeexplore.ieee.org/abstract/document/6942058),” European Solid-State Circuits Conference, Venice, Italy, 2014.

Index

• Analog IC Design in Nanoscale CMOS Short Course(https://www.p-brane.com/nano/blogpost1300-Analog-IC-Design-in-Nanoscale-CMOS-Short-Course)
• Analog IC Design Course Homework 1 SIMetrix Edition(https://www.p-brane.com/nano/blogpost1302-Analog-IC-Design-Course-Homework-1-SIMetrix-Edition)
• Analog IC Design Course Homework 2 SIMetrix Edition(https://www.p-brane.com/nano/blogpost1303-Analog-IC-Design-Course-Homework-2-SIMetrix-Edition)