The Analog IC Design in Nanoscale CMOS short course is scheduled for September 7 to October 1, 2021 virtually from the University of Limerick. The short course consists of eight 1.5 hour lectures followed by a half hour question and answer session. The course is taught by Professor Tony Chan Carusone.
- Lecture 1 - CMOS Device Scaling & Modeling 7th Sept. 2021 Device scaling, short-channel length effects, analog design on bulk CMOS technologies below 30nm.
- Lecture 2 - Advanced CMOS Technologies: SOI & FinFET 10th Sept. 2021 Impact on transistor model parameters, analog FOM & layout strategies. Reliability effects.
- Lecture 3 - Amplifier Design in Nanoscale CMOS 14th Sept. 2021 Design of current mirrors & amplifier circuits. Suitable OTA topologies for low supply-voltage.
- Lecture 4 - References, Regulators & Power Integrity 17th Sept. 2021 Diff. reference circuits & voltage regulation. Power distribution in ICs. Power integrity analysis.
- Lecture 5 - Nanoscale CMOS Clocking 21st Sept. 2021 Jitter sources, amplification & power-supply-induced jitter. CMOS buffering & clock distribution.
- Lecture 6 - Dynamic Comparators & Amplifiers 24th Sept. 2021 Applications of dynamic amplifiers (as integrators) in high-speed receivers. Dynamic comparators.
- Lecture 7 - ADC-Based Receivers in Nanoscale CMOS 28th Sept. 2021 High-speed ADCs: folding-flash, binary search & CT pipelined. Combatting mismatch & applications.
- Lecture 8 - Real-Life Cautionary Tales 1st Oct. 2021 Common design & layout errors, integrating large designs, power & clock routing, non-working chips.
The following references provides some background for the course.
- Textbook chapter 1 for lectures 1 and 2
- Textbook chapter 7.4 for lecture 4
- IEEE articles shown below
- Analog Integrated Circuit Design 2nd Edition by Tony Chan Carusone
- D. Mohammadi, et al, “A 7-GS/s 5-Bit Continuous-Time Pipelined Binary-Search Flash ADC in 28-nm CMOS,” IEEE Solid-State Circuits Letters, Sept. 2020.
- B. Dehlaghi*, et al, “A 1.41pJ/b 56Gb/s PAM-4 Receiver Using Enhanced Transition Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS,” IEEE Solid-State Circuits Letters, 2019.
- L. Wang, et al, “A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET,” IEEE Journal of Solid-State Circuits, Dec 2018.
- L. Wang, et al, “A 4GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16nm FinFET,” IEEE Transactions on Circuits and Systems II, Dec. 2017.
- S. Shahramian, et al, “Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5 us,” IEEE Journal of Solid-State Circuits, pp. 3192-3203, Nov 2016.
- B. Dehlaghi, et al, “A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication,” IEEE Journal of Solid-State Circuits, pp. 2690-2701, Nov 2016.
- D. Dunwell, et al, “Modeling Oscillator Injection Locking Using the Phase Domain Response,” IEEE Transactions on Circuits and Systems I, 2013, pp. 2823-2833, November 2013.
- K. Yamamoto, et al, “A 1-1-1-1 MASH Delta-Sigma Modulator with Dynamic Comparator-Based OTAs,” IEEE Journal of Solid-State Circuits, vol. 49, no. 8, pp. 1866-1883, August 2012.
- P. Chen, et al, “All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs,” IEEE International Symposium on Circuits and Systems, Seville, Spain, October 2020.
- S. Shahramian*, et al, “A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS,” International Solid-State Circuits Conference, February 2019.
- S. Chen, et al, “All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters,” International Symposium on Circuits and Systems, May 2018.
- S. Shahramian, et al, “Chip-Level Power Integrity Methodology for High-Speed Serial Links,” DesignCon, Santa Clara, California, January 2018.
- A. Sharif-Bakhtiar, et al, “Low-Power CMOS Receivers for Short Reach Optical Communication,” Custom Integrated Circuits Conference, Austin, Texas, May 2017.
- L. Wang, et al, “Time Interleaved C-2C SAR ADC with Background Timing Skew Calibration in 65nm CMOS,” European Solid-State Circuits Conference, Venice, Italy, 2014.
- Analog IC Design in Nanoscale CMOS Short Course
- Analog IC Design Course Homework 1 SIMetrix Edition
- Analog IC Design Course Homework 2 SIMetrix Edition