7 nm Model Parameters
Since the frequency response in homework 2 produced a unity gain frequency for the shorter gate length that wasn't higher than the long gate length FinFET, I suspect a problem with the model or the way I'm using it so I investigated the model further. The following model parameters were used for this investigation and for homework 3.
parameter  Model  Value  units

Fin Length  L  20.0  nm

Number of fins  NFIN  3 

Number of fingers  NFGR  1 

Fin Height  HFIN  32.0  nm

Fin Thickness  TFIN  6.5  nm

Fin Pitch  FPITCH  27.0  nm

Fin Width, 1 fins  W  70.5  nm

Fin Width, 3 fins   211.5  nm

W/L for 3 fins   10.6 

Gate oxide thickness  EOT  1  nm 
The fin width was computed as NFIN (2 HFIN + TFIN) where HFIN is the fin height and TFIN is the fin thickness using the .model variables. This makes W/L = 10.6 for a FinFet with 3 fins.
Using methods described in the course and in the book, the performance parameters for the 7 nm models were extracted. I haven't found a references to confirm the performance values yet.
Parameter  NMOS  PMOS  Units

μC_{OX}  156.6  110.2  μA/V^{2}

V_{t}  230  210  mV

λ  0.1795  0.3563  1/V

λL  0.0036  0.0071  μm/V

C_{OX}    fF/μm^{2}

n  1.05  1.02 

θ  2.94  1.92  V

C_{OV}/W = L_{OV}C_{OX}  0.16  0.16  fF/μm

C_{db}/W ≈ C_{Sb}  5.5*10^{8}  5.6*10^{8}  fF/μm 
The 7 nm models from the PTM website [1] are define with the .model function and have more parameters defined compared to the modified (simplified) model provided for the course. These models use the BSIMCMG [2] model. The PTM website indicates that the model process maximum supply voltage is 700 mV. The homework, however, specifies V
_{DS} = 800 mV in the problems so was used for the solutions. The solutions are based on the materials presented in the course and the book Analog Integrated Circuit Design [3].
The sections below show how the parameters were determined and how the SIMetrix simulator was setup to make the measurements. Mathematica was used to add the line guides to estimate the projection of the g
_{m} slopes to the xaxis and to the projections of maximum g
_{m}.
NMOS μ_{n}C_{OX}, V_{t}, subthreshold slope, n, and θ
The schematic used for finding μ
_{n}C
_{OX}, V
_{t}, subthreshold slope, n, and θ is shown below.
The top plot in the figure below shows g
_{m}/I
_{D} vs V
_{GS}. The minimum was found to be 62.4 mV/decade using
Measure > 8 Minimum
. n=1.05 was found using Ln(10)(nKT/q) = subthreshold slope (i.e n = 62.4 mV/(2.3kT/q)).
The middle plot shows g
_{m} vs V
_{GS}. The linear slope of g
_{m} is μ
_{n}C
_{OX}(W/L) and was used to determine μ
_{n}C
_{OX} at 156.6 μA/V
^{2} for W/L = 211.5/20. The projection of the slope to the xaxis gives V
_{t} at 230 mV. The voltage V
_{GS} at the intersection of where the projection of the g
_{m} slope to a line that is parallel to where g
_{m} flattens is used to determine V
_{eff}. At that point V
_{eff} = 1/(2θ). Solving for θ, θ = 2.9/V [4].
The bottom plot shows I
_{D} in the active region.
PMOS μ_{p}C_{OX}, V_{t}, subthreshold slope, n, and θ
The schematic used for finding μ
_{p}C
_{OX}, V
_{t}, subthreshold slope, n, and θ is shown below.
The top plot in the figure below shows g
_{m}/I
_{D} vs V
_{GS}. The minimum was found to be 60.8 mV/decade using
Measure > 8 Minimum
. n=1.02 was found using Ln(10)(nKT/q) = subthreshold slope (i.e n = 60.8 mV/(2.3kT/q)).
The middle plot shows g
_{m} vs V
_{GS}. The linear slope of g
_{m} is μ
_{p}C
_{OX}(W/L) and was used to determine μ
_{p}C
_{OX} at 110.2 μA/V
^{2} for W/L = 211.5/20. The projection of the slope to the xaxis gives V
_{t} at 210 mV. The voltage V
_{GS} at the intersection of where the projection of the g
_{m} slope to a line that is parallel to where g
_{m} flattens is used to determine V
_{eff}. At that point V
_{eff} = 1/(2θ). Solving for θ, θ = 1.9/V
The bottom plot shows I
_{D} in the active region.
NMOS λL
The schematic below was used determine λ.
The top plot in the figure below shows g
_{ds}/I
_{D} and the bottom shows I
_{D} vs V
_{DS} for V
_{GS} = 300 mV, 500 mV, 800 mV, and 1 V. To generate a useful plot g
_{ds}/I
_{D}, the
Choose Analysis
V
_{DS} sweep can't start a 0 V so that g
_{ds}/I
_{D} doesn't become infinite.
g
_{ds}/I
_{D} and I
_{D} vs V
_{DS} were plotted again but only for V
_{GS} = 500 mV to determine λ and λL. Recall that
$$g_{ds}=\frac{\partial I_d}{\partial V_{DS}}=\lambda (\frac{\mu_n C_{OX}}{2})(\frac{W}{L})V_{eff}^2=\lambda I_{Dsat}=\lambda I_d$$
In short, g
_{ds}/I
_{D} = λ and was sampled in the middle of the active range at V
_{DS} = 654 mV as the start of the active region occurs at V
_{DSsat} = V
_{eff} = 500 mV  230 mV = 270 mV. λ = 0.1795/V and λL = 0.00359 μm/V [5].
PMOS λL
g
_{ds}/I
_{D} and I
_{D} vs V
_{DS} were plotted again but only for V
_{GS} = 500 mV to determine λ and λL. Recall that $$g_{ds}=\frac{\partial I_d}{\partial V_{DS}}=\lambda (\frac{\mu_p C_{OX}}{2})(\frac{W}{L})V_{eff}^2=\lambda I_{Dsat}=\lambda I_d$$
In short, g
_{ds}/I
_{D} = λ and was sampled in the middle of the active range at V
_{DS} = 693 mV as the start of the active region occurs at V
_{DSsat} = V
_{eff} = 500 mV  210 mV = 290 mV. λ = 0.3563/V and λL = 0.00713 μm/V.
NMOS C_{OV}/W and C_{db}/W
The schematic below was used to determine C
_{OV}/W.
The plot below shows the gate current I
_{g} vs frequency. The gate current is function of frequency and I
_{g} = 2πfV
_{g}C
_{OV}. Solving for C
_{OV}, C
_{OV} = I
_{g}/(2πfV
_{g}) with f = 10 MHz and V
_{g} = 2 V because the AC source produces a 1 V peak output. I
_{g} = 4.25 nA at 10 MHz so C
_{OV}/W = 0.16 fF/μm for the 211.5 nm gate width [6].
The schematic below was used to find C
_{db}/W.
The plot below shows the body current I
_{b} vs frequency. The body current is function of frequency and I
_{b} = 2πfV
_{b}C
_{b} where C
_{b} = C
_{db}+C
_{sb}. Solving for C
_{b}, C
_{b} = I
_{b}/(2πfV
_{bs}) with f = 10 MHz and V
_{b} = 2 V because the AC source produces a 1 V peak output. I
_{b} = 2.95 fA at 10 MHz so C
_{b}/W = 1.1*10
^{7} fF/μm for the 211.5 nm gate width. For C
_{db} = C
_{sb} = C
_{b}/2 = 5.5*10
^{8} fF/μm [7].
PMOS C_{OV}/W and C_{db}/W
The schematic below was used to determine C
_{OV}/W.
The
Simulate > Choose Analysis
setup for the AC analysis shown below.
I
_{g} = 4.25 nA at 10 MHz so C
_{OV}/W = 0.16 fF/μm for the 211.5 nm gate width.
The schematic below was used to find C
_{db}/W.
I
_{b} = 3.099 fA at 10 MHz so C
_{b}/W = 1.13*10
^{7} fF/μm for the 211.5 nm gate width. For C
_{db} = C
_{sb} = C
_{b}/2 = 5.57*10
^{8} fF/μm.
NMOS I_{D} and R_{in} vs V_{GS}
The gate and drain for the nmos_lvt and nmos_rvt transistors are connected together to simulated the IV curve of a diode connected transistor that is used as part of a current mirror. The MOSFET connected in this way isn't really a diode but its IV curve behaves like an diode IV curve because the V
_{GS} = V
_{DS} and the transistor operates in the active region. The I
_{D} vs V
_{DS} is
$$I_d=\frac{1}{2}\mu_n C_{OX} \frac{W}{L} (V_{GS}V_t)^2 = \frac{1}{2} \mu_n C_{OX} \frac{W}{L}(V_{DS}V_t)^2$$
Solving for V
_{DS} gives [8]
$$V_{DS}=\sqrt{\frac{I_d}{\frac{1}{2} \mu_n C_{OX} \frac{W}{L}}}+V_t$$
Using the model parameters in the table above at 100 μA, V
_{DS} = 577.5 mV for the nmos_lvt transistor, and V
_{DS} = 609.2 mV at 100 μA in the simulation. This represents a 32 mV error between the simulation and the calculation.
Transistor  V_{DS}  Simulation  Units

nmos_lvt  577.5  609.2  mV 
The schematic below shows the diode connected nmos_lvt and nmos_rvt FinFETs in single and stacted configurations.
The bottom plot in the figure below shows the I
_{D} vs V
_{GS} for the nmos_lvt and nmosrvt transistors. The top two traces are the single gatedrain connected transistors, and the bottom two traces are the stacked transistors. The REF cursor is set at the I
_{D} = 100 μA for the single nmos_lvt transistor. The B cursor is set at the I
_{D} = 100 μA for the stacked nmos_lvt transistors. The middle plot shows g
_{m} for the transistors. The single transistors have the higher g
_{m} compared with the stacked transistors. The top plot shows the output resistance. The cursors was placed at 100 μA for the nmos_lvt device and the V
_{DS} is 609.2 mV and an resistance of 6.093 kOhms. The stacked nmos_lvt transistors have a V
_{DS} of 814.0 mV and a resistance of 8.138 kOhms.
PMOS I_{D} and R_{in} vs V_{GS}
The simulation was repeated for the pmos_lvt and pmos_rvt transistors for both single and stacked configurations. The schematic for this simulation is shown below.
The bottom plot in the figure below shows the I
_{D} vs V
_{GS} for the nmos_lvt and nmosrvt transistors. The top two traces are the single gatedrain connected transistors, and the bottom two traces are the stacked transistors. The REF cursor is set at the I
_{D} = 100 μA for the single nmos_lvt transistor. The B cursor is set at the I
_{D} = 100 μA for the stacked nmos_lvt transistors. The middle plot shows g
_{m} for the transistors. The single transistors have the higher g
_{m} compared with the stacked transistors. The top plot shows the output resistance. The cursors was placed at 100 μA for the nmos_lvt device and the V
_{DS} is 650.5 mV and an resistance of 6.505 kOhms. The stacked nmos_lvt transistors have a V
_{DS} of 902.5 mV and a resistance of 9.021 kOhms.
The figures below shows how the
Choose Analysis
and
Define Curve
configuration panels were setup to produce the plot above.
Index
References
[1]:
ASU Predictive Technology Model (PTM)
[2]:
BSIM Group Berkeley BSIMCMG Model
[3]: T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd Edition. Wiley, 2011.
[4]: T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd Edition. Wiley, 2011. see pg. 28, 30, 47.
[5]: T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd Edition. Wiley, 2011. see pg. 29.
[6]:
45nm CMOS process – Learning Microelectronics
[7]:
45nm CMOS process – Learning Microelectronics.
[8]: T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd Edition. Wiley, 2011. see pg. 129.